Cypress CapSense CY8C20396 Instrukcja Użytkownika Pobierz pdf (Strona 2)

CY8C20x36/46/66, CY8C20396

Document Number: 001-12696 Rev. *D Page 2 of 34

Block Diagram

CAPSENSE

SYSTEM

1K/2K

SRAM

Interrupt

Controller

Sleep and

Watchdog

Multiple Clock Sources

Internal Low Speed Oscillator (ILO)

6/12/24 MHz Internal Main Oscillator

(IMO)

PSoC CORE

CPU Core (M8C)

Supervisory ROM (SROM)

8K/16K/32K Flash

Nonvolatile Memory

SYSTEM RESOURCES

SYSTEM BUS

Analog

Reference

SYSTEM BUS

Port 3 Port 2 Port 1 Port 0

CapSense

Module

Global Analog Interconnect

1.8/2.5/3V

LDO

Analog

Mux

Two

Comparators

I2C

Slave

SPI

Master/

Slave

POR

and

LVD

USB

System

Resets

Internal

Voltage

References

Three 16-Bit

Programmable

Timers

PWRSYS

(Regulator)

Port 4

Digital

Clocks

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