Cypress CY7C1041DV33 Instrukcja Użytkownika Strona 1

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Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05473 Rev. *E Revised July 17, 2008
CY7C1041DV33
4 Mbit (256K x 16) Static RAM
Features
Pin and function compatible with CY7C1041CV33
High speed
t
AA
= 10 ns
Low active power
I
CC
= 90 mA at 10 ns (industrial)
Low CMOS standby power
I
SB2
= 10 mA
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II packages
Functional Description
The CY7C1041DV33
[1]
is a high performance CMOS Static RAM
organized as 256K words by 16 bits. To write to the device, take
Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte
LOW Enable (BLE
) is LOW, then data from IO pins (IO
0
to IO
7
)
is written into the location specified on the address pins (A
0
to
A
17
). If Byte HIGH Enable (BHE) is LOW, then data from IO pins
(IO
8
to IO
15
) is written into the location specified on the address
pins (A
0
to A
17
).
To read from the device, take Chip Enable (CE
) and Output
Enable (OE
) LOW while forcing the Write Enable (WE) HIGH. If
BLE
is LOW, then data from the memory location specified by
the address pins appears on IO
0
to IO
7
. If BHE is LOW, then data
from memory appears on IO
8
to IO
15
. See the Truth Table on
page 9 for a complete description of read and write modes.
The input and output pins (IO
0
to IO
15
) are placed in a high
impedance state when the device is deselected (CE
HIGH),
outputs are disabled (OE
HIGH), BHE and BLE are disabled
(BHE
, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid
array (FBGA) package.
14
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K × 16
A
0
A
11
A
13
A
12
A
A
A
16
A
17
A
9
A
10
IO
0
–IO
7
OE
IO
8
–IO
15
CE
WE
BLE
BHE
Logic Block Diagram
Note
1. For guidelines on SRAM system design, refer to the “System Design Guidelines” Cypress application note, available at www.cypress.com.
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Strona 1 - 4 Mbit (256K x 16) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #: 38-05473 Rev. *E Revised July 17, 2008CY7

Strona 2

CY7C1041DV33Document #: 38-05473 Rev. *E Page 10 of 13 Ordering InformationSpeed(ns) Ordering CodePackageDiagram Package TypeOperatingRange10 CY7C104

Strona 3

CY7C1041DV33Document #: 38-05473 Rev. *E Page 11 of 13 Figure 11. 44-Pin (400-mil) Molded SOJ (51-85082)Figure 12. 44-Pin TSOP II (51-85087)Package

Strona 4

CY7C1041DV33Document #: 38-05473 Rev. *E Page 12 of 13 Document History PageDocument Title: CY7C1041DV33 4 Mbit (256K x 16) Static RAMDocument Number

Strona 5

CY7C1041DV33© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconducto

Strona 6

CY7C1041DV33Document #: 38-05473 Rev. *E Page 2 of 13 Selection GuideDescription –10 (Industrial) –12 (Automotive)[2]UnitMaximum Access Time 10 12 ns

Strona 7

CY7C1041DV33Document #: 38-05473 Rev. *E Page 3 of 13 Maximum RatingsExceeding maximum ratings may shorten the useful life of thedevice. These user g

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CY7C1041DV33Document #: 38-05473 Rev. *E Page 4 of 13 Capacitance[6]Parameter Description Test Conditions Max UnitCINInput Capacitance TA = 25°C, f =

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CY7C1041DV33Document #: 38-05473 Rev. *E Page 5 of 13 AC Switching Characteristics Over the Operating Range[8]Parameter Description–10 (Industrial) –

Strona 10 - CY7C1041DV33

CY7C1041DV33Document #: 38-05473 Rev. *E Page 6 of 13 Data Retention Characteristics Over the Operating RangeParameter Description Conditions[14]Min

Strona 11

CY7C1041DV33Document #: 38-05473 Rev. *E Page 7 of 13 Figure 5. Read Cycle No. 2 (OE Controlled)[17, 18]Figure 6. Write Cycle No. 1 (CE Controlled)

Strona 12

CY7C1041DV33Document #: 38-05473 Rev. *E Page 8 of 13 Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)Figure 8. Write Cycle No. 3 (WE Controlled

Strona 13

CY7C1041DV33Document #: 38-05473 Rev. *E Page 9 of 13 Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW)Truth TableCE OE WE BLE BHEIO0–IO7IO8–IO15M

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