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February 19, 2008 Document No. 001-15342 Rev. ** 1

with FX2LP

Implementing an 8-Bit Asynchronous Interface

Application Note Abstract

This application note discusses how to configure the General Programmable Interface (GPIF) and slave FIFOs of the EZ-USB

FX2LP™ to implement an 8-bit asynchronous interface. The GPIF is a programmable 8 or 16-bit parallel interface that reduces

system costs by providing a glueless interface between the EZ-USB FX2LP and different types of external peripherals. The

GPIF allows the EZ-USB FX2LP to perform local bus mastering to external peripherals implementing a wide variety of protocols.

For example, EIDE/ATAPI, printer parallel port (IEEE P1284), Utopia, and other interfaces are supported using the GPIF block

of the EZ-USB FX2LP. In this example, it masters the slave FIFO interface of another EZ-USB FX2LP.

This implementation uses the GPIF Designer (an utility Cypress provides to create GPIF waveform descriptors) to design the

application specific physical layer. The firmware is based on the Cypress EZ-USB FX2LP firmware ‘frameworks’. A hardware

setup of two back-to-back EZ-USB FX2LP boards is also used, one acting as a master and another as a slave. Familiarity with

the EZ-USB FX2LP development kit, examples and documentation on the development kit CD-ROM, and chapters 9 (EZ-USB

FX2LP Slave FIFOs) and 10 (GPIF) of the EZ-USB FX2LP Technical Reference Manual is assumed

Introduction

The objective of this application note is to:

■ Demonstrate a glueless interface to an 8-bit peripheral

data bus (the FIFO of a slave EZ-USB FX2LP).

■ Use EZ-USB FX2LP to transfer data to and from the pe-

ripheral (slave EZ-USB FX2LP) and the USB host.

This application note discusses the necessary hardware con-

nections, internal register settings, and 8051 firmware imple-

mented to execute data transactions over the interface and

across the USB bus.

Figure 1. Hardware Connection Diagram

AN6077

Author: Sonia Gandhi

Associated Project: No

Associated Part Family: CY7C68013A

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Software Version: None

Associated Application Notes: None

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Podsumowanie treści

Strona 1 - Introduction

February 19, 2008 Document No. 001-15342 Rev. ** 1 with FX2LPImplementing an 8-Bit Asynchronous InterfaceApplication Note AbstractThis application n

Strona 2 - Creating GPIF Waveforms

February 19, 2008 Document No. 001-15342 Rev. ** 10 AN6077 }#define GPIFTRIGWR 0#define GPIFTRIGRD 4#define GPIF_EP2 0#define GPIF_EP4 1#define GP

Strona 3

February 19, 2008 Document No. 001-15342 Rev. ** 11 AN6077 // setup GPIF transaction count SYNCDELAY;

Strona 4 - Firmware Architecture

February 19, 2008 Document No. 001-15342 Rev. ** 12 AN6077 // RDY0=1, when peripheral is "not empty"// drive FIFOADDR lines

Strona 5 - Psuedocode for Master IN

February 19, 2008 Document No. 001-15342 Rev. ** 13 AN6077 }BOOL TD_Suspend( void ) { // Called before the device goes into suspend mode

Strona 6 - Expanded Master IN Code

February 19, 2008 Document No. 001-15342 Rev. ** 14 AN6077{ // Called when a Set Interface command is received EP0BUF[ 0 ] = AlternateSetting;

Strona 7 - Firmware for the Slave

February 19, 2008 Document No. 001-15342 Rev. ** 15 AN6077 EZUSB_IRQ_CLEAR( ); USBIRQ = bmURES; // Clear URES IRQ}void ISR_Susp( void ) i

Strona 8 - Code Listing for Master Side

February 19, 2008 Document No. 001-15342 Rev. ** 16 AN6077}void ISR_Ep1pingnak( void ) interrupt 0{}void ISR_Ep2pingnak( void ) interrupt 0{}void I

Strona 9

February 19, 2008 Document No. 001-15342 Rev. ** 17 AN6077}void ISR_Ep8fflag( void ) interrupt 0{}void ISR_GpifComplete( void ) interrupt 0{}void I

Strona 10 - [+] Feedback

February 19, 2008 Document No. 001-15342 Rev. ** 18 AN6077 // PINFLAGSxx EPxFIFOIRQ // EPxFIFOIE GPIFIRQ // GPIFIE GPIFAD

Strona 11

February 19, 2008 Document No. 001-15342 Rev. ** 19 AN6077 EP2FIFOCFG = 0x10; // AUTOOUT=1, WORDWIDE=0 SYNCDELAY; EP6FIFOCFG = 0x0C

Strona 12

February 19, 2008 Document No. 001-15342 Rev. ** 2 AN6077GPIF Master Pin DescriptionsThe GPIF pin names, descriptions, and their uses are dis-cusse

Strona 13

February 19, 2008 Document No. 001-15342 Rev. ** 20 AN6077 EP0BUF[ 0 ] = Configuration; EP0BCH = 0; EP0BCL = 1; return(TRUE); // H

Strona 14

February 19, 2008 Document No. 001-15342 Rev. ** 21 AN6077 USBIRQ = bmSOF; // Clear SOF IRQ}void ISR_Ures( void ) interrupt 0{ if ( EZUS

Strona 15

February 19, 2008 Document No. 001-15342 Rev. ** 22 AN6077}void ISR_Ep4inout( void ) interrupt 0{}void ISR_Ep6inout( void ) interrupt 0{}void ISR_E

Strona 16

AN6077Cypress Semiconductor198 Champion CourtSan Jose, CA 95134-1709Phone: 408-943-2600Fax: 408-943-4730http://www.cypress.com© Cypress Semiconductor

Strona 17

February 19, 2008 Document No. 001-15342 Rev. ** 3 AN6077Figure 2 shows the GPIF Designer view of the FIFO Readwaveform.FIFOWRWhen creating the FIF

Strona 18

February 19, 2008 Document No. 001-15342 Rev. ** 4 AN6077Figure 4. FIFO Read Waveform in gpif.cFigure 5. FIFO Write Waveform in gpif.c8051 Firmwa

Strona 19

February 19, 2008 Document No. 001-15342 Rev. ** 5 AN6077The firmware uses the AUTO mode for both IN and OUTtransfers. This means that the maximum

Strona 20

February 19, 2008 Document No. 001-15342 Rev. ** 6 AN6077 IOA = 0x80; xFIFOTC_OUT = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL );

Strona 21

February 19, 2008 Document No. 001-15342 Rev. ** 7 AN6077 if( EP68FIFOFLGS & 0x01 ) { // EP6FF=1, when fifo "full"

Strona 22

February 19, 2008 Document No. 001-15342 Rev. ** 8 AN6077Code Listing for Master Side#pragma NOIV // Do not generate interrupt v

Strona 23

February 19, 2008 Document No. 001-15342 Rev. ** 9 AN6077 // EP4 and EP8 are not used in this implementation SYNCDELAY; // E

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