Cypress CY62128EV30 Instrukcja Użytkownika Pobierz pdf (Strona 6)

CY62128EV30

Document #: 38-05579 Rev. *D Page 6 of 11

Switching Waveforms

Figure 2. Read Cycle 1 (Address transition controlled)

[15, 16]

Figure 3. Read Cycle No. 2 (OE controlled)

[10, 16, 17]

Figure 4. Write Cycle No. 1 (WE controlled)

[10, 15, 18, 19]

PREVIOUS DATA VALID DATA VALID

OHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

ACE

DOE

LZOE

LZCE

HIGH IMPEDANCE

HZOE

HZCE

IMPEDANCE

HIGH

ADDRESS

DATA OUT

SUPPLY

CURRENT

DATA VALID

PWE

SCE

HZOE

ADDRESS

DATA IO

NOTE

Notes

15. The device is continuously selected. OE

, CE

= V

, CE

= V

16. WE

is HIGH for read cycle.

17. Address valid before or similar to CE

transition LOW and CE

transition HIGH.

18. Data IO is high impedance if OE

= V

19. If CE

goes HIGH or CE

goes LOW simultaneously with WE HIGH, the output remains in high impedance state.

20. During this period, the IOs are in output state. Do not apply input signals.

[+] Feedback

1 2 3 4 5 6 7 8 9 10 11

CY62128EV30 1
THEVENIN EQUIVALENT 4
51-85056-*D 9
51-85094-*D 10

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