Cypress CY62128EV30 Instrukcja Użytkownika Pobierz pdf (Strona 12)

CubeSat Kit PPM B1 Rev. A

August 2009 – document Rev. B

CONNECTORS

Item Description Source Part Number Application

100-pin,

hermaphroditic

Samtec LSS-150-01-L-DV PPM connector (standard, +3mm)

This connector information is provided for reference only.

PROGRAMMING & DEBUGGING

PPM B1 provides one interface for programming and debugging – the popular and low-cost USB Debug

Adapter from Silicon Devices. It provides another debugging adapter for simple user I/O. Both are

implemented via Flexible Printed Circuit (FPC) connectors on the PPM.

8-pin FPC connector J1 is for the USB Debug Adapter. Via Pumpkin’s JFPC-C8051 adapter, customers

can connect the USB Debug Adapter with its 10-pin 2x5 0.100” pitch dual-inline headers. The

JFPC-C8051 connects to PPM B1 via an 8-conductor FPC cable.

6-pin FPC connector J2 is for user debug purposes, and is compatible with 6-conductor FPC cables.

Customers who wish to use the user port must fabricate their own adapter.

Its pin assignments are

described below

PIN DESCRIPTIONS – J2 User Debug Connector

Pin I/O Description

I/O

IO.23. From P3.7 (U1.47). Can be used as general-purpose I/O.

I/O

IO.22. From P3.6 (U1.48). Can be used as general-purpose I/O.

I/O

IO.21. From P3.5 (U1.49). Can be used as general-purpose I/O.

I/O

SCL_SYS. From P0.7 (U1.55). Normally used for an I2C monitor. Can be used as

general-purpose I/O if properly configured.

I/O

SDA_SYS. From P0.6 (U1.46). Normally used for an I2C monitor. Can be used as

general-purpose I/O if properly configured.

-- Digital ground.

NOTES

Through the C8051's Priority Crossbar Decoder (XBAR) the user can enable digital peripherals and have

them appear at certain I/O pins on U1. To be compatible with the CubeSat Kit Motherboard (MB), the

UART0, SPI0 (4-wire mode), SMB0 and UART1 peripherals must be enabled in the XBAR. Enabling

these four peripherals maps will cause their I/O to appear properly on IO.[7..0], SCL_SYS and

SDA_SYS (i.e., on the first 10 mappable C8051 I/O pins). Users are free to enable any of the other

functions available through the XBAR, mapping them to P1.2 or beyond.

N.B.: SPI0 must remain configured as 4-wire SPI, even if the Slave Select (NSS) functionality is not

required. Configuring SPI0 for three-wire mode will map the SCL_SYS, SDA_SYS, TX1 and RX1 functions

to the wrong pins of U1, the MB and the CubeSat Kit bus connector. Where NSS functionality is not

required, P0.5 can be treated as GPIO by appropriate register configuration.

U1's VREF (Bandgap Voltage Reference Output) is left unconnected on Rev A of PPM B1. Future

revisions may offer a user-fittable zero-ohm jumper from VREF to VREF0/VREF2/VREFD.

Crystal X3 is not normally fitted, as the C8051F120 has an internal precision 24.5MHz clock source and

PLL. Should the customer desire a different clock source, X3 can be fitted.

Provisions for 0805-size

loading caps C3 and C4 are included on the PPM B1 PCB.

Alternatively, a Pumpkin JFPC-PIC24 programming adapter can be used, as it maps 6 FPC pins to a 6-pin 1x6 0.100" pitch single

in-line header.

E.g. ECS P/N ECS-xxx-20-5PXDN.

1 2 ... 7 8 9 10 11 12 13 14

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