Cypress CY14B256L Instrukcja Użytkownika Pobierz pdf (Strona 13)

CY14B256L

Document Number: 001-06422 Rev. *H Page 13 of 18

Hardware STORE Cycle

Parameter Alt Description

CY14B256L

Unit

Min Max

PHSB

HLHX

Hardware STORE Pulse Width 15 ns

DELAY

[17]

HLQZ ,

BLQZ

Time Allowed to Complete SRAM Cycle 1 70

[18, 19]

Soft Sequence Processing Time 70 us

Switching Waveforms

Figure 12. Hardware STORE Cycle

Figure 13. Soft Sequence Processing

[18, 19]

$GGUHVV $GGUHVV $GGUHVV $GGUHVV

6RIW6HTXHQFH

&RPPDQG

$GGUHVV

6RIW6HTXHQFH

&RPPDQG

Notes

17. Read and Write cycles in progress before HSB

are given this amount of time to complete.

18. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

19. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command.

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