Cypress DCT-1D Podręcznik Użytkownika Pobierz pdf (Strona 10)

CHAPTER 1. THE SYST EM

Device

System

Gates

CLB

(1 CLB = 4 slices = Max 128 bits)

Multiplier

Blocks

SelectRAM Blocks

DCMs

Max I/O

Pads

(1)

Array

Row x Col. Slices

Maximum

Distributed

RAM Kbits

18 Kbit

Blocks

Max R AM

(Kbits)

XC2V40 40K 8 x 8 256 8 4 4 72 4 88

XC2V80 80K 16 x 8 512 16 8 8 144 4 120

XC2V250 250K 24 x 16 1,536 48 24 24 432 8 200

XC2V500 500K 32 x 24 3,072 96 32 32 576 8 264

XC2V1000 1M 40 x 32 5,120 160 40 40 720 8 432

XC2V1500 1.5M 48 x 40 7,680 240 48 48 864 8 528

XC2V2000 2M 56 x 48 10,752 336 56 56 1,008 8 624

XC2V3000 3M 64 x 56 14,336 448 96 96 1,728 12 720

XC2V4000 4M 80 x 72 23,040 720 120 120 2,160 12 912

XC2V6000 6M 96 x 88 33,792 1,056 144 144 2,592 12 1,104

XC2V8000 8M 112 x 104 46,592 1,456 168 168 3,024 12 1,108

Table 1.1: Virtex-II table. XC2V4000 is our FPGA.

1.2.3 Virtex-II 4000 FPGA

The most important circuit on the board is of course the mighty Virtex-II 4000 FPGA,

[5]. The table 1.1 gives some details of this impressive circuit, which is shipped in an

1152 pin BGA (ball grid array).

The internal conﬁgurable logic in the FPGA includes four major elements organized

in a regular array:

• CLBs (Conﬁgurable Logic Blocks):

This is the programmable logic used to build combinatorial and sequential logic.

The FPGA contains 80 × 72 = 5760 CLBs. Each CLB is made up of 4 slices,

see Figure 1.4.

• Multipliers:

The FPGA contains 120 18 × 18-bit multipliers. These are used for the ALU in

the OR1200 CPU.

• Block RAMs:

The FPGA contains 120 18 kbit RAMs. These are typically used for cache

memories inside the CPU, FIFOs in the UART and Ethernet controller.

• DCMs (Digital Clock Managers):

The FPGA contains 12 DCMs. The DCMs can divide/multiply the input clock

frequency. We use a DCM to transform the input 40 MHz to 25 MHz.

A ﬂoorplan of the Virtex-II is shown in Figure 1.3.

The CLBs are organized in an array and connected to a switching matrix. Each

CLB comprises 4 slices, which are connected locally. Each slice includes two 4-input

function generators, carry logic, multiplexers and two storage elements, see Figure 1.4.

The function generator can be programmed as a 4-input lookup table (LUT), 16-bit

RAM or 16-bit variable-tap shift register.

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 81 82

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