Cypress DCT-1D Podręcznik Użytkownika Pobierz pdf (Strona 26)

CHAPTER 2. LAB TASK 0 - BUILD A UART IN VERILOG

2.3 Exercises

Preparation task 1

Draw a HW diagram of the UART. Use simple components like counters, registers,

shift registers, and state machines.

Laboration task 1

a) Translate your HW diagram into Verilog code.

b) Simulate your design in ModelSim.

c) Synthesize your design, program the FPGA and test run your design.

2.3.1 Commands

To start the simulator, use the command make sim_lab0. To generate a bitﬁle to

program the FPGA with use make lab0.

To conﬁgure the FPGA with a .bit file, use make prog_lab0.

2.3.2 A User Constraint File

You will need the User Constraint File shown in Listing 2.2. The exact same signals

and names mentioned in Listing 2.2 must be present in the interface declaration of you

top module. Comment out the lines that you don’t use. (This ﬁle is included in the lab

skeleton as lab0.ucf.)

Listing 2.2: User constraints ﬁle for your UART

NET "clk_i" LOC = " AK19" ; / / 40 MHz i n t h i s l a b

NET "rst_i" LOC = "C2" ; / / SW1 ( r e d ) on g r e e n f l e x o

NET "send_i" LOC = "B3" ; / / SW2 ( b l a c k ) on g r e e n f l e x o

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Cypress DCT-1D Podręcznik Użytkownika Strona 26