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CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUS
3.6 Useful Commands
We have prepared a makefile based build system that is responsible for both building
the monitor firmware and synthesizing the hardware from the RTL source code. You
can use it on the Linux computers in Muxen 1. The following targets will be useful for
you:
• make lab1 Creates a bit file of the computer in this lab task.
• make sim_lab1 Launches Modelsim on the “lab1” system.
• make sim_uart Launches Modelsim on your UART.
• make dafk Creates a bit file of the complete system.
• make sim Launches Modelsim on the complete system.
• make simfiles Recompiles all source files for use with Modelsim but does
not launch Modelsim itself. This is mainly useful if you already have Modelsim
running and want to try out some changes to your source code. This way you
don’t need to close Modelsim, it is enough to issue a restart command in
Modelsim.
• make clean Removes intermediate files and backup files.
• make updatebit Compiles the monitor and updates dafk.bit, and lab1.bit
with the new monitor. This way you don’t need to resynthesize the design to test
changes in your monitor. The updated bit file is named updated_dafk.bit for
dafk.bit and so on.
We also have some utilities that you might be interested in. The first of these is
download.sh which you can use to download your design. (You may use this script
either in Windows or Linux. In Windows it will invoke Impact in batch mode and in
Linux it will invoke xc3sprog.) Invoke it as in the following example:
utils/download.sh dafk.bit
Another utility is designed to highlight the error and warning messages in the var-
ious reports that the Xilinx flow will output. Use it on (for example) the synthesis
report with the following command:
utils/checklogs.pl synthdir/dafk.syr | less -r
The other alternative is to pipe the output of make through checklogs:
make dafk.bit | utils/checklogs.pl
3.6.1 Synthesis Reports
If you use make, the following files will be of special interest to you: (look in /nobackup/local/<your
name>/
- Laboratory manual for TSEA44 1
- Contents 3
- CONTENTS 4
- The system 7
- 1.2 Hardware 8
- 1.2. HARDWARE 9
- 1.2.3 Virtex-II 4000 FPGA 10
- 1.3 Open RISC 11
- CHAPTER 1. THE SYST EM 12
- 1.3.3 OR1200 CPU 13
- 1.3.5 Memory Controller 15
- 1.3.6 Ethernet Controller 15
- 1.4 Software 16
- 1.4. SOFTWARE 17
- 1.4.4 µClinux 20
- Lab task 0 - Build a UART in 23
- 2.2.2 The hardware 24
- 2.2.3 A simple testbench 24
- 2.2. A SIMPLE UART 25
- 2.3 Exercises 26
- Preparation task 1 26
- Laboration task 1 26
- 2.4 gtkterm usage 27
- Wishbone bus 29
- Master Slave 30
- 3.2.1 A Wishbone Interconnect 31
- 3.3 A Simple Computer 32
- Preparation task 2 33
- Preparation task 3 34
- Preparation task 4 34
- Laboration task 2 35
- 3.4 A Benchmark Program 36
- 3.4. A BENCHMARK PROGRAM 37
- Preparation task 5 38
- Laboration task 3 39
- 3.6 Useful Commands 40
- 3.7.1 A Note on Volatile 41
- Lab task 2 - Design a JPEG 43
- Preparation task 6 44
- 4.2.2 Distributed RAMs 45
- Preparation task 7 46
- Laboration task 4 47
- Laboration task 5 47
- 4.3 Introduction to µClinux 47
- Laboration task 6 47
- Laboration task 7 48
- 4.4 Introduction to jpegfiles 48
- Preparation task 8 49
- Laboration task 8 50
- Laboration task 9 50
- 4.5 Timestamps 50
- 4.6 Quantization 51
- Preparation task 9 52
- 4.7 Tips and tricks 53
- Lab task 3 55
- WAITREADY 56
- GETBLOCK 56
- WAITREADY_LAST RELEASEBUS 56
- 5.1.2 jpeg_dma.sv 56
- Preparation task 10 58
- Laboration task 10 58
- Laboration task 11 58
- Laboration task 12 58
- CHAPTER 5. LAB TASK 3 60
- Chapter 6 61
- Preparation task 11 62
- Preparation task 12 62
- 6.2 Adding a New Instruction 62
- 6.3 Proposed Architecture 63
- 6.4 Hardware Implementation 64
- 6.5 Software Implementation 65
- Laboration task 13 67
- Laboration task 14 67
- 6.7 Tips and tricks 68
- 6.9 Beyond tsea44 70
- Bibliography 71
- BIBLIOGRAPHY 72
- Open RISC Reference Platform 73
- A.2 Interrupts 74
- The Wishbone specification 75
- B.2 Interface signals 76
- −WSS−CLK_I 77
- B.5 System Verilog Interface 79
- Tips & Trix 81
- APPENDIX C. TIPS & TRIX 82
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