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CHAPTER 5. LAB TASK 3

IDLE

WAITREADY

GETBLOCK

WAITREADY_LAST RELEASEBUS

Figure 5.1: The proposed state diagram for the DMA accelerator.

In Figure 5.1 there is a state diagram which is suitable for the DMA accelerator. The

states are described below:

• IDLE:

The DMA module is not doing anything.

• GETBLOCK:

The DMA module is fetching an 8x8 block. Once the block is fetched we go to

the WAITREADY state and starts the DCT transform.

• RELEASEBUS:

The DMA accelerator has to release the bus regularly so that other components

can access it. You should do this for every line of a macroblock that you read.

• WAITREADY:

In this state we wait until the program tells us that it has read the result of the

transform by writing to the control register.

• WAITREADY_LAST:

Same as WAITREADY except that we go to the IDLE state when done.

5.1.2 jpeg_dma.sv

The interface to the jpeg_dma module consists of a wishbone master interface, a sim-

pliﬁed wishbone slave port and some control signals that are connected to the DCT

accelerator in the jpeg_top module. A simpliﬁed view of the proposed architecture is

shown in ﬁgure 5.2. Some of the most important signals are described below:

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Cypress DCT-1D Podręcznik Użytkownika Strona 56