Cypress DCT-1D Podręcznik Użytkownika Pobierz pdf (Strona 23)

Chapter 2

Lab task 0 - Build a UART in

Verilog

2.1 Introduction

In this introductory lab exercise you will learn the HDL Verilog. We r equire that you

are familiar with another HDL, typically VHDL. In our opinion hardware design is

done by drawing hardware diagrams, so that the programming in Verilog is just a ﬁnal

simple translation step!

You will also get (re)acquainted with the tools used in this course, ModelSim and

make (or Xilinx Project Navigator).

2.2 A simple UART

2.2.1 The RS232 protocol

In this exercise you shall design a simple RS232 transceiver in Verilog. We assume

that the serial port of the FPGA board is connected to a PC, where a terminal program

is running. This is typically gtkterm if you are using Linux or Teraterm if you are

running in Windows. The bit rate should be ﬁxed 115200 bits/s. Your design shall use

the parameters 8N1, that is 8 message bits, no parity bit and 1 stop bit, see Figure 2.1.

Messages are sent and received with LSB ﬁrst. Furthermore your UART shall support

full duplex operation, that is be able to transmit and receive at the same time.

1

0 0 0 0 0 01 stopstart

t

Figure 2.1: The letter A (0x41). Time per bit is 8.68 µs.

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 81 82

Brak uwag

Cypress DCT-1D Podręcznik Użytkownika Strona 23