Cypress DCT-1D Podręcznik Użytkownika Pobierz pdf (Strona 12)

CHAPTER 1. THE SYST EM

LUT

inputs

FXINA MUXFX

FXINB

FF/LAT

REV

CLK

MUXF5

LUT

inputs

FF/LAT

REV

CLK

a) b)

Figure 1.4: a) Virtex-II slice conﬁguration b) Detail of slice (top half).

1.3.2 Structure of the Verilog code

The structure of the Verilog code closely resembles the block diagram shown in Fig-

ure 1.5. Components outside the FPGA are simulated. Here is a list of the hierarchy

instantiated in dafk_tb:

• phy0: Simulation model of the Ethernet physical to logic level chip

• videomem: Simulation model of the video memory

• mysram: Simulation model of the SRAM

• sdram0: Simulation model of the SDRAM

• dafk_top: The code to be synthesized in the FPGA

– sys_sig_gen: Generates clock and reset signals

– or1200_top: The OR1200 CPU

– pkmc_top: Memory controller

– rom0: The boot monitor code and vector table resides here

– uart2: UART 16550

– eth3: Ethernet controller

– dvga: VGA controller

– pia: Simple parallel port

– jpg0: DCT accelerator

– perf: Performance counters

– leela: Camera module

– wb_conbus: The wishbone bus

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 81 82

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Cypress DCT-1D Podręcznik Użytkownika Strona 12